64 lines
3.0 KiB
C++
64 lines
3.0 KiB
C++
#pragma once
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#include <cstdint>
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#define SYS_MAP_DEV_START_ADDR 0x0000000000 // 0 ~ 128MB
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#define SYS_MAP_DEV_END_ADDR 0x0007ffffff // 128MB
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#define SYS_MAP_SRAM_START_ADDR 0x0008000000 // 128MB ~ 146MB
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#define SYS_MAP_SRAM_END_ADDR 0x00091fffff // 18MB
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#define SYS_MAP_CCU_REG_START_ADDR 0x000a230000 //
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#define SYS_MAP_CCU_REG_SIZE 0x00004000 // 16KB
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#define SYS_MAP_DDR_START_ADDR 0x0100000000
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#define SYS_MAP_DDR_END_ADDR 0x3fffffffff
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#define CCU_MAP_DEV_START_ADDR SYS_MAP_DEV_START_ADDR
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#define CCU_MAP_DEV_END_ADDR SYS_MAP_DEV_END_ADDR
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#define CCU_MAP_SRAM_START_ADDR SYS_MAP_SRAM_START_ADDR
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#define CCU_MAP_SRAM_END_ADDR SYS_MAP_SRAM_END_ADDR
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#define CCU_MAP_CCU_REG_START_ADDR 0x000a000000
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#define CCU_MAP_CCU_REG_SIZE SYS_MAP_CCU_REG_SIZE
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#define CCU_MAP_VB_START_ADDR 0x000a100000
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#define CCU_MAP_VB_END_ADDR 0x000a1fffff
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#define CCU_MAP_DDR_START_ADDR 0x000a200000
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#define CCU_MAP_DDR_END_ADDR 0x0fffffffff
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#define CCU_DDR_BOUDARY 0x000a200000 // 162MB
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#define CCU_DDR_OFFSET 0x00f5e00000 // 4GB - 162MB
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#define CCU_DM0_OUTSTANDING 32
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#define MASK_UINT32 0xffffffff
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#define MASK_UINT64 0xffffffffffffffff
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// sys map
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// ============== sync mem map ==============
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#define MEM_ADDR_SYS_MAP_SYNC_UNIT_BASE 0x00a080000
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#define MEM_ADDR_SYNC_UNIT_SIZE (4 * 1024)
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// ============== cpu job queue ==============
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#define CSR_ADDR_SYS_MAP_JOB_QUEUE_BASE 0x00a23b000
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#define CSR_ADDR_JOB_QUEUE_SIZE (4*1024)
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// ==============ccu cfg==============
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#define CSR_ADDR_SYS_MAP_CCU0_BASE SYS_MAP_CCU_REG_START_ADDR
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#define CSR_ADDR_SYS_MAP_CCU1_BASE SYS_MAP_CCU_REG_START_ADDR + SYS_MAP_CCU_REG_SIZE
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#define CSR_ADDR_CCU_SIZE (16*1024)
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// ==============d2d cfg==============
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#define CSR_ADDR_SYS_MAP_D2D_BRIDGE_BASE 0x00a2e0000
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#define CSR_ADDR_D2D_BRIDGE_SIZE (4* 1024)
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// reg cmd registers
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#define CSR_ADDR_SYS_MAP_D2D_REG_CMD_BASE 0x00a2e0400
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#define CSR_ADDR_D2D_REG_CMD_SIZE (1*1024)
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// data cmd registers
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#define CSR_ADDR_SYS_MAP_D2D_DATA_CMD_BASE 0x00a2e0800
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#define CSR_ADDR_D2D_DATA_CMD_SIZE (1*1024)
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// ============== ddr and sram mem map ==============
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#define MEM_ADDR_CCU_MAP_SRAM_BASE ( 128UL*1024*1024) // 128 MB
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#define MEM_ADDR_CCU_MAP_DDR_BASE ( 162UL*1024*1024) // 162 MB
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#define MEM_ADDR_SYS_MAP_SRAM_BASE MEM_ADDR_CCU_MAP_SRAM_BASE
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#define MEM_ADDR_SYS_MAP_DDR_BASE ( 4L * 1024*1024*1024)
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#define MEM_ADDR_DDR_SIZE (256L * 1024*1024*1024) // 38 bit, 256GB
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#define MEM_ADDR_SRAM_SIZE ( 18*1024*1024) // 18 MB
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#define SYS_PMU_BASE_ADDR 0x0a238000 |