#pragma once
#include <cstdint>

#define SYS_MAP_DEV_START_ADDR          0x0000000000    // 0 ~ 128MB
#define SYS_MAP_DEV_END_ADDR            0x0007ffffff    // 128MB
#define SYS_MAP_SRAM_START_ADDR         0x0008000000    // 128MB ~ 146MB
#define SYS_MAP_SRAM_END_ADDR           0x00091fffff    // 18MB
#define SYS_MAP_CCU_REG_START_ADDR      0x000a230000    // 
#define SYS_MAP_CCU_REG_SIZE            0x00004000      // 16KB
#define SYS_MAP_DDR_START_ADDR          0x0100000000
#define SYS_MAP_DDR_END_ADDR            0x3fffffffff

#define CCU_MAP_DEV_START_ADDR          SYS_MAP_DEV_START_ADDR
#define CCU_MAP_DEV_END_ADDR            SYS_MAP_DEV_END_ADDR
#define CCU_MAP_SRAM_START_ADDR         SYS_MAP_SRAM_START_ADDR
#define CCU_MAP_SRAM_END_ADDR           SYS_MAP_SRAM_END_ADDR
#define CCU_MAP_CCU_REG_START_ADDR      0x000a000000
#define CCU_MAP_CCU_REG_SIZE            SYS_MAP_CCU_REG_SIZE
#define CCU_MAP_VB_START_ADDR           0x000a100000
#define CCU_MAP_VB_END_ADDR             0x000a1fffff
#define CCU_MAP_DDR_START_ADDR          0x000a200000
#define CCU_MAP_DDR_END_ADDR            0x0fffffffff

#define CCU_DDR_BOUDARY                 0x000a200000    // 162MB
#define CCU_DDR_OFFSET                  0x00f5e00000    // 4GB - 162MB

#define CCU_DM0_OUTSTANDING             32

#define MASK_UINT32                     0xffffffff
#define MASK_UINT64                     0xffffffffffffffff

// sys map
// ============== sync mem map ==============
#define MEM_ADDR_SYS_MAP_SYNC_UNIT_BASE         0x00a080000
#define MEM_ADDR_SYNC_UNIT_SIZE                 (4 * 1024)

// ============== cpu job queue ==============
#define CSR_ADDR_SYS_MAP_JOB_QUEUE_BASE         0x00a23b000
#define CSR_ADDR_JOB_QUEUE_SIZE                 (4*1024)

// ==============ccu cfg==============
#define CSR_ADDR_SYS_MAP_CCU0_BASE              SYS_MAP_CCU_REG_START_ADDR
#define CSR_ADDR_SYS_MAP_CCU1_BASE              SYS_MAP_CCU_REG_START_ADDR + SYS_MAP_CCU_REG_SIZE
#define CSR_ADDR_CCU_SIZE                       (16*1024)

// ==============d2d cfg==============
#define CSR_ADDR_SYS_MAP_D2D_BRIDGE_BASE       0x00a2e0000
#define CSR_ADDR_D2D_BRIDGE_SIZE                (4* 1024)
// reg cmd registers
#define CSR_ADDR_SYS_MAP_D2D_REG_CMD_BASE       0x00a2e0400
#define CSR_ADDR_D2D_REG_CMD_SIZE               (1*1024)
// data cmd registers
#define CSR_ADDR_SYS_MAP_D2D_DATA_CMD_BASE      0x00a2e0800
#define CSR_ADDR_D2D_DATA_CMD_SIZE              (1*1024)

// ============== ddr and sram mem map ==============
#define MEM_ADDR_CCU_MAP_SRAM_BASE              (       128UL*1024*1024)  // 128 MB
#define MEM_ADDR_CCU_MAP_DDR_BASE               (       162UL*1024*1024)  // 162 MB
#define MEM_ADDR_SYS_MAP_SRAM_BASE              MEM_ADDR_CCU_MAP_SRAM_BASE

#define MEM_ADDR_SYS_MAP_DDR_BASE               (  4L * 1024*1024*1024)
#define MEM_ADDR_DDR_SIZE                       (256L * 1024*1024*1024)  // 38 bit, 256GB
#define MEM_ADDR_SRAM_SIZE                      (         18*1024*1024)  // 18 MB
#define SYS_PMU_BASE_ADDR                       0x0a238000